Search - verilog cpu

[Other] cpu的VERILOG描述

Description: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
Platform: | Size: 369497 | Author: 陈俊 | Hits:

Description: 这是arm7处理器的verilog全代码，仔细研究一下，会对CPU和verilog均有很大的裨益。-This is ARM7 processor Verilog-wide code carefully, CPU and Verilog will have great benefits.
Platform: | Size: 38050 | Author: 王云 | Hits:

[Other resource] cpu

Description: 精简指令cpu，用verilog编写，详细的教程
Platform: | Size: 214766 | Author: 郑欲 | Hits:

[Other resource] cpu

Description: Verilog实现的CPU程序，简单应用哈
Platform: | Size: 2829 | Author: liu | Hits:

[Other resource] cpu

Description: 初学cpu设计（完全教程）包括verilog代码以及文档说明那个
Platform: | Size: 367165 | Author: hjx | Hits:

[Other resource] CPU

Description: 使用verilog作为CPU设计语言实现单数据通路五级流水线的CPU。具有32个通用寄存器、一个程序计数器PC、一个标志寄存器FLAG，一个堆栈寄存器STACK。存储器寻址粒度为字节。数据存储以32位字对准。采用32位定长指令格式，采用Load/Store结构，ALU指令采用三地址格式。支持有符号和无符号整数加、减、乘、除运算，并支持浮点数加、减、乘、除四种运算，支持与、或、异或、非4种逻辑运算，支持逻辑左移、逻辑右移、算术右移、循环右移4种移位运算，支持Load/Store操作，支持地址/立即数加载操作，支持无条件转移和为0转移、非0转移、无符号>转移、无符号<转移、有符号>转移、有符号<转移等条件转移。
Platform: | Size: 43474 | Author: haotianr | Hits:

[Other resource] CPU

Description: 以前在学校里的课程设计，使用verilog编写的一个CPU程序，可以下板子
Platform: | Size: 6507 | Author: 熊浩 | Hits:

[VHDL-FPGA-Verilog] MIIPS CPU VHDL源代码

Description: 该文件是一个较简单的MIIPS CPU的Verilog 源代码
Platform: | Size: 94951 | Author: wangboch@126.com | Hits:

[SourceCode] risc cpu

Description: risc 8 bit cpu core verilog
Platform: | Size: 139464 | Author: maxwellnul | Hits:

[VHDL-FPGA-Verilog] t80

Description: Configurable cpu core that supports Z80, 8080 and gameboy instruction sets
Platform: | Size: 41984 | Author: 吴毅 | Hits:

[DSP program] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key-- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424384 | Author: 呈一 | Hits:

[Other] control0

Description: systemverilog编写的cpu读写mem程序-SystemVerilog prepared by the cpu readers mem procedures
Platform: | Size: 1024 | Author: 王晓波 | Hits:

[VHDL-FPGA-Verilog] 16_risc_cpu

Description: 一个支持精简指令的16位的risc cpu，可综合-a directive to support the streamlining of the 16 RISC CPU can be integrated
Platform: | Size: 163840 | Author: 董 | Hits:

[VHDL-FPGA-Verilog] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2048 | Author: wyl | Hits:

[Other] u26a_spice

Description: ddr2控制器一些源码，控制时序及怎样通过嵌入式cpu来进行控制的实例-ddr2 Controller some source code, and how to control the timing of embedded cpu passed to the control of the examples
Platform: | Size: 297984 | Author: | Hits:

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[Other] cpu的VERILOG描述

[Other resource] arm7-verilog

[Other resource] cpu

[Other resource] cpu

[Other resource] cpu

[Other resource] CPU

[Other resource] CPU

[VHDL-FPGA-Verilog] MIIPS CPU VHDL源代码

[SourceCode] risc cpu

[VHDL-FPGA-Verilog] t80

[DSP program] TMS320C54x DSP 的cpu和外围设备

[Other] control0

[VHDL-FPGA-Verilog] 16_risc_cpu

[VHDL-FPGA-Verilog] bfm

[Other] u26a_spice

[ARM-PowerPC-ColdFire-MIPS] leg_source

[VHDL-FPGA-Verilog] RiscCpu

[VHDL-FPGA-Verilog] mips-cpu-master

[VHDL-FPGA-Verilog] 实验一多路选择器与CPU辅助模块设计

[VHDL-FPGA-Verilog] 单周期CPU大作业-2020

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